Can you imagine the benefits of routing a PCB Design with a A-SAP™ 25-micron trace and space?
Just to name a few; complex pin outs could require fewer layers and a reduction in costly lamination cycles, the overall footprint of the PCB could be dramatically reduced, or conversely, additional electronics functionality could be fit into an existing footprint.
This benefits alone is exciting, but NOW just imagine if that 25-micron trace and space technology could be integrated into a PCB stack-up that included both very high-density feature sizes along with traditional subtractive etch technology? Yes, A-SAP™ processes blend easily with all the traditional circuit fabrication processes.
Imagine This…A-SAP™ layers
To kick start your imagination picture this: a 10-layer printed circuit board design, pushing the traditional design limits of the subtractive etch process, requires stacked or staggered micro vias and three lamination cycles. We have all been there, right? Nail-biting hoping for good yields knowing you have designed something that will push boundaries of even your more trustworthy, high technology fabricators.
Here is the good news. This design could be re-imagined using 25-micron trace and space on critical pin out layers, while keeping other layers as originally designed, using the best of both PCB processes and resulting in a reduction in overall size and thickness, specifically, a reduction to 8 layers but perhaps even more importantly, a reduction to just one lamination cycle. Simplifying the fabrication process, increasing yields and reducing costs. Something to think about!
Averatek’s A-SAP™, a Semi-Additive PCB technology does just that. A-SAP™ is currently being licensed to printed circuit board fabricators and is now commercially available for prototype and low to medium volume production. This technology enables the fabrication of 25-micron line and space and below and is relatively easily integrated with traditional PCB fabrication processes, eliminating the need for costly capital investment while allowing these fabricators to leap-frog past traditional PCB capabilities.
This ultra-high-density packaging and interconnect solution can reduce size and weight by 90% over current state of the art processes within the US, is shown to have significant RF advantages over traditional subtractive-etch processing and is opening-up design possibilities that were previously unavailable.
A future blog will go into detail about how the semi-additive PCB process fits within the framework of traditional PCB fabrications processes, but as a sneak peek, rather than creating the circuitry from a traditional copper clad laminate and etching the copper that is not required, this semi-additive process starts by removing all the copper from the base laminate, and then adding copper to the bare substrate creating the specified circuit pattern.
The key lies in the very thin electroless copper layer, significantly thinner than copper foils. Once the circuit image is created, electrolytic copper finishes the circuit plating. Because the initial electroless copper is so thin, much thinner than any of the available foil options, the flash etching to remove the unnecessary copper does not noticeably impact the circuit pattern.
This process results in traces with horizontal sidewalls rather than trapezoidal in shape, realizing benefits in both size and RF properties. Once the circuit pattern is created, the circuit layers follow most of the traditional PCB fabrication steps involved in the subtractive etch process.
Visit our information center at www.averatek.com to learn more about the A-SAP™ process and the benefits of designing with 25 micron feature sizes. Please reach out to me at tara@averatek.com if you have any questions.